The present invention generally relates to pattern forming methods in which a plurality of patterns are successively overlapped and exposed on a substrate, and more particularly to a pattern forming method which uses a multi-level alignment and is suited for application to semiconductor device production which requires high accuracy.
Recently, the use of semiconductor integrated circuits is rapidly increasing and there is a strong demand to improve the integration density of the semiconductor integrated circuits. In order to meet this demand, there is active research and development in photolithography techniques. Accurate alignment techniques are very important in determining integration density improving the resolution by way of which fine patterns are formed.
According to conventional techniques, a lower layer which is the subject of the alignment is formed on a substrate and a photoresist layer is formed on this lower layer. Thereafter, a main pattern and an alignment mark pattern are simultaneously exposed so as to form on the lower layer the main pattern and a set of alignment marks which have a fixed positional relationship to the main pattern. Then, an upper layer which is to be aligned and a photoresist layer are formed on the lower layer. The positions of the alignment marks on the lower layer are measured, and a mask for the upper layer is exposed after moving the substrate so that the positions of the alignment marks match predetermined fixed positions relative to the mask. When forming a multi-level pattern, the above described procedure is repeated to successively make the alignment.
The accuracy of conventional alignment techniques may be unclustered by referring to FIG. 1. For the sake of convenience, the accuracy of conventional techniques will be explained in connection with a one-dimensional, alignment, however, a similar phenomena of course occur in the case of two-dimensional alignments. A layer which is the subject of the process and a photoresist layer are combined and referred to as a first layer, and an nth layer will be denoted by the designation Ln. Three layers L1 through L3 are successively exposed in this example. Of course, the example is not limited to exposure by a light and the exposure may be made by an electron beam or the like.
First, the first layer L1 is formed and a pattern PI and an alignment mark MI are formed as part of the first later L1 A coordinate of a reference point on the first layer L1 is denoted by X1. A formed, a mask for the second layer L2 is aligned with alignment mark MI of the first layer L1 and this mask is exposed to form a second layer L2 on layer L1. A reference point on the second layer L2 is denoted by X2. When normal alignment techniques used in this way, the reference point X2 of the second layer L2 has an average value which is by approximation equal to the reference point X1 of the first layer L1 and is a random variable in conformance with a normal distribution of a variance d.sub.2.sup.2. Next, a mask for the third layer L3 is aligned with the alignment mark MII of the second layer L2 and this mask is exposed to thus form layer L3. A reference point on the third layer L3 is denoted by X3. The reference point X3 of the third layer L3 has an average value which is by approximation equal to the reference point X2 of the second layer L2 and is a random variable in conformance with a normal distribution of a variance d.sub.3.sup.2.
The variance of the positional error X1-X2 between the layers L1 and L2 is expressed as the d.sub.2.sup.2, and variance of the positional error X2-X3 between the layers L2 and L3 is expressed as d.sub.3.sup.2. The variance of the positional error between the layers L1 and L3 thus becomes d.sub.2.sup.2 +d.sub.3.sup.2. This variance d.sub.2.sup.2 +d.sub.3.sup.2 of the positional error between the layers L1 and L3 has a great deteriorating effect on the alignment accuracy in connection with so-called indirect alignment.
According to conventional alignment techniques, indirect alignment accuracy deteriorates as the distance between the two layers increases during the alignment sequence. Positional error between layers is a serious problem for semiconductor devices having complex structures. For this reason, the patterns of semiconductor devices must be laid out to include margins which take into account the alignment error, but these measures alignment error prevents further improvement of the integration density of the semiconductor device.